FIG. 1 shows a typical configurational example of a conventional direct conversion receiver. An RF (Radio Frequency) signal received through an antenna not shown is input to input terminal 1 and amplified by low noise amplifier (to be referred to hereinbelow as LNA) 2, then is branched into two routes. The RF signals branched into two routes are mixed (multiplied) with local signals (to be referred to hereinbelow as LO signals) cos ωt and sin ωt that are input through local signal input terminals 4a and 4b, in down-conversion mixers (to be referred to hereinbelow as mixers) 3a and 3b, respectively, and down-converted. The LO signals cos ωt and sin ωt are signals having phases that are different by 90 degrees from each other, and the frequency of the LO signals cos ωt and sin ωt is set at the same frequency as the carrier frequency of a desired RF signal. In this way, baseband signals can be obtained by a single down-conversion with mixers 3a and 3b. 
The baseband signals output from mixer 3a and 3b are converted into digital signals by variable-gain amplifiers 5a, 5b, 7a and 7b, low-pass filters (to be referred to hereinbelow as LPFs) 6a and 6b for channel section and analog/digital converters (to be referred to hereinbelow ADCs) 8a and 8b. The digital signals converted by ADCs 8a and 8b are processed by baseband signal processor (BB) 9. Gain controller (gain setter) 10 controls the gains of LNA 2 and variable-gain amplifiers 5a, 5b, 7a and 7b as appropriate, based on the result of the time slot, BER (bit error rate) data, reception intensity, etc., of the processed result by baseband signal processor 9.
In the aforementioned direct conversion receiver, before filtering out the components other than channel signal by LPFs 6a and 6b, mixers 3a and 3b perform down-conversion into baseband signals. Accordingly, under circumstances in which jamming waves exist, it is impossible to obtain high enough gain at the stages prior to mixers 3a and 3b. For this reason, the intensity of the desired signal after down-conversion through mixers 3a and 3b basically becomes weaker, hence the influence that DC offset exerts on the signal after down-conversion becomes relatively greater.
DC offset arises due to variations of mixers 3a and 3b. Other than this, several mechanisms that cause DC offset have been known.
Main mechanisms that generate DC offset in a conventional signal processing unit will be described using FIGS. 2 to 5. Here, in FIGS. 2 to 5, reference numeral 3 denotes 3a and 3b in FIG. 1 and reference numeral 4 denotes 4a and 4b in FIG. 1.
In the signal processing unit shown in FIG. 2, a LO signal input into mixer 3 from local signal input terminal 4 passes through path 11 due to leak etc., into the RF port of mixer 3, and the LO signals of the same source are mixed, to thereby generate a DC offset. This DC offset is so-called static offset, which will not vary depending on time.
In the signal processing unit shown in FIG. 3, a LO signal input from local signal input terminal 4 passes through path 12 and enters LNA 2 from the input terminal 1 side into the RF port of mixer 3, and the LO signals of the same source are mixed, to thereby generate a DC offset. The amount of this DC offset varies in accordance with the gain set at LNA 2. Accordingly, when the gain of LNA 2 is set up immediately after the start of reception of an RF signal, the amount of DC offset varies. Further, there is a case in which the LO signal that passes to input terminal 1 of LNA 2 flows back to the antenna and is radiated once to the space and then reenters LNA 2 and mixer 3 through the antenna. The DC offset in this case is a so-called dynamic DC offset, which varies the amount of DC offset in a dynamic manner depending on the surrounding environment.
In the signal processing unit shown in FIG. 4, part of the RF signal received by the antenna passes through route 13 and passes to the side of local signal input terminal 4 of mixer 3 so that RF signals of the same source are mixed to thereby generate the DC offset. This DC offset conspicuously appears when there is a strong jamming wave within the vicinity of the frequency range of the desired RF signal. Since the intensity of the received jamming wave varies, being affected by fading, etc., the DC offset shown in FIG. 4 is a dynamic DC offset.
In the signal processing unit shown in FIG. 5, part of the RF signal amplified by LNA 2 passes through route 14 and passes to the side of local signal input terminal 4 of mixer 3 so that RF signals of the same source are mixed to thereby generate the DC offset. This DC offset has both the property of a dynamic DC offset in which the amount of the DC offset varies dynamically, being affected by fading etc. and the property of varying the-amount of DC offset stepwise under the influence of the gain change of LNA 2. The amount of this DC offset also varies depending on the second-order distortion of mixer 3.
Next, techniques for canceling (removing) DC offset in the conventional signal processing unit will be described with reference to FIGS. 6 to 9. Here, in FIGS. 6 to 9, reference numeral 3 indicates 3a or 3b in FIG. 1, reference numeral 4 indicates 4a or 4b in FIG. 1, and reference numeral 5 indicates 5a or 5b in FIG. 1.
In the signal processing unit shown in FIG. 6, a capacitance 15 for cutting off the DC component of the signal output from mixer 3 is provided on the output side of mixer 3.
Similar to FIG. 6, in the signal processing unit shown in FIG. 7, high-pass filter (to be referred to hereinbelow as HPF) 16 for cutting off the DC component of the signal output from mixer 3 is provided on the output side of mixer 3. Capacitance 15 and HPF 16 both have the high-pass property for permitting only the frequency component having a cutoff frequency or greater to pass therethrough. Conventionally, the cutoff frequency of HPF 16 is selected low enough so that no desired component will be lost, and it is designed so as to be as high as about 0.1% of the transmission rate in the communications system to which the signal processing unit is applied (see [B. Razavi, “A 2.4-GHz CMOS Receiver for TEEE 802.11 Wireless LAN's” IEEE JSSC, Vol. 34 No. 10, pp. 1382-1385 October 1999]).
The signal processing units shown in FIGS. 6 and 7 still have the common drawbacks that there is a possibility that part of the desired component of the signal may be lost and that it becomes difficult to achieve both removal of DC offset and preservation of the desired signal component when the amount of DC offset varies with time.
That is, in order to deal with dynamic DC offset in which the amount of DC offset varies depending on time, it is necessary to set the cutoff frequency of HPF 16 higher. However, if the cutoff frequency of HPF 16 is set higher, the desired component of the signal will also be lost, so that BER may degrade to an impermissible level, depending on the modulation scheme of the received signal.
In the signal processing unit shown in FIG. 8, feedback element 17 for performing DC servo feedback is added to variable-gain amplifier 5. Variable-gain amplifier 5 and feedback element 17 have the combined function of an HPF and an amplifier. The signal processing unit shown in FIG. 8 has the same drawbacks as those of the signal processing units shown in FIGS. 6 and 7.
The signal processing unit shown in FIG. 9 adopts such a scheme in which the DC offset contained in the signal output from mixer 3 is taken in by ADC 18 and the amount of DC offset at signal processor 19 is detected, then the DC offset is cancelled by digital/analog converter (to be referred to hereinbelow as DAC) 20. Here, in FIG. 9, a feed-forward type configuration is shown but a feed-back type configuration may be possible.
There is one known method as in the above scheme, in which the amount of DC offset is detected within an undesired reception time slot and the signal for canceling the DC offset is fixed in a desired reception time slot. However, this scheme entails drawbacks in that hardware configuration becomes complex, a control signal for canceling DC offset in synchronism with a received time slot needs to be generated at the baseband signal processor and, in that, if a variation in DC offset occurs during the desired received time slot, it is impossible to deal with that variation, and with others.
As another conventional technology for canceling DC offset, there is a technology disclosed in Japanese Patent Application Laid-open 8-316998 (to be referred to hereinbelow as patent document 1). This technology is one that basically uses a HPF. The characteristics of this technology are that the received signal level (=received signal intensity) is monitored and if the monitored received signal level has varied greater than a predetermined value, the time constant of the HPF is shortened. If the received signal level varies, DC offset variation such as the following (1) and (2) will occur:    (1) variation in DC offset attributed to second-order distortion of the mixer; and    (2) variation in DC offset caused by gain switching of a variable-gain amplifier.
Accordingly, based on the technology disclosed in patent document 1, it is possible to deal with DC offset variations (1) and (2).
However, according to the technology disclosed in patent document 1, since variation in DC offset is indirectly observed in the form of a variation of the received signal level, there is the drawback that a suitable control cannot be always performed. That is, depending on the mechanism by which DC offset is generated in the signal processing unit and the setting conditions of the signal processing unit, there are possibilities that the time constant of the HPF is switched to be shorter even though that DC offset is unvaried and that the time constant remains long even though that DC offset is varied. Further, in the technology disclosed in patent document 1, a separate device for generating a signal for switching the time constant of the HPF based on the monitored received signal level is needed, so that there is the drawback that the hardware configuration becomes complicated.
As another conventional technology for canceling DC offset, there is a technology disclosed in Japanese Patent Application Laid-open 11-186874 (to be referred to hereinbelow as patent document 2). In this technology, an amplifier having differential inputs is provided; one terminal of this amplifier serves as a signal input terminal and the other terminal is supplied with a negative feedback signal from the differential output. A non-linear element which presents a low gain for a small amplitude signal and a high gain for a large amplitude signal is interposed in the negative feedback path. Based on this, it is disclosed that the response time for converging the DC level of the signal output from the signal processing unit can shortened.
However, in the technology disclosed in patent document 2, there is an obvious drawback that when responding the signal input to the signal processing unit contains a constant DC offset. For example, consider a case where the DC offset voltage contained in the input signal is much higher than the ideal middle-point potential and a desired signal component having a smaller amplitude than the DC offset has been superimposed over the signal. In this case, in the apparatus based on the technology disclosed by patent document 2, the DC voltage of the negative feedback signal also comes to have a voltage close to the aforementioned DC offset voltage or much higher than the ideal middle-point potential. That is, the DC level of the signal output from the non-linear element inserted in the negative feedback path becomes a voltage level rather apart from the ideal middle-point potential. As a result, this non-linear element takes a high-gain state so that the cutoff frequency of the HPF remains at a high level.
To sum up, in the technology disclosed in patent document 2, the time constant of the HPF is determined by the absolute value of the DC offset contained in the signal input to the signal processing unit. Accordingly, it is impossible to converge the DC level of the signal output from the signal processing unit and to keep the time constant of the HPF long.
As another conventional technology for canceling DC offset, there is a technology disclosed in Japanese Patent Application Laid-open 2003-224488 (to be referred to hereinbelow as patent document 3). This technology is one that uses a HPF. This technology is characterized in that if a case corresponds to any one of the following (1) to (4), the case is determined to be a period during which the DC offset is likely to be increased and the time constant of the HPF is set shorter than that at the time of normal operation, to thereby deal with DC offset variation:    (1) when the gain of a variable-gain amplifier is changed;    (2) a period after the power to the receiver has been activated;    (3) a period immediately after a circuit is started up during intermittent reception; and    (4) a period immediately after a different frequency measurement in a W-CDMA system has been started.
However, in the technology disclosed in patent document 3, since the cutoff frequency of the HPF is controlled by detecting any of the above (1) to (4), there is a possibility that the cutoff frequency of the HPF is switched even if there is no variation in DC offset. Further, a controller for switching the time constant of the HPF is needed, hence there occurs the drawback that the hardware configuration becomes complicated.
As has been described heretofore, in conventional technologies, it is impossible to achieve both countermeasures against dynamic DC offset and transmission without loss of the desired signal component at the same time.